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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ssm2160/ssm2161 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1996 6- and 4-channel, serial input master/balance volume controls functional block diagram power supply and reference generator vca ch1 in ch1 out clk data ld write v+ v v ref ? 5-bit channel dac vca ch2 in ch2 out ? 5-bit channel dac vca ch3 in ch3 out ? 5-bit channel dac vca ch4 in ch4 out ? 5-bit channel dac vca ch5 in ch5 out ? 5-bit channel dac vca ch6 in ch6 out ? 5-bit channel dac 7-bit master dac shift register and address decoder step size adjust ch set mstr set mstr out features clickless digitally controlled level adjustment ssm2160: six channels ssm2161: four channels 7-bit master control gives 128 levels of attenuation 5-bit channel controls give 32 levels of gain master/channel step size set by external resistors 100 db dynamic range automatic power on mute excellent audio characteristics: 0.01% thd+n 0.001% imd (smpte) C90 dbu noise floor C80 db channel separation 90 db snr single and dual supply operation applications home theater receivers surround sound decoders circle surround* and ac-3* decoders dsp soundfield processors hdtv and surround tv audio systems automotive surround sound systems multiple input mixer consoles and amplifiers general description the ssm2160 and ssm2161 allow digital control of volume of six and four audio channels, respectively, with a master level control and individual channel controls. low distortion vcas (voltage controlled amplifiers) are used in the signal path. by using controlled rate-of-change drive to the vcas, the click- ing associated with switched resistive networks is eliminated in the master control. each channel is controlled by a dedicated 5-bit dac providing 32 levels of gain. a master 7-bit dac feeds every control port giving 128 levels of attenuation. step sizes are nominally 1 db and can be changed by external resistors. channel balance is maintained over the entire master control range. upon power-up, all outputs are automatically muted. a three- or four-wire serial data bus enables interfacing with most popular microcontrollers. windows * software and an evaluation board for controlling the ssm2160 are available. the ssm2160 can be operated from single supplies of +10 v to +20 v or dual supplies from 5 v to 10 v. the ssm2161 can be operated from single supplies of +8.5 v to +20 v (for automotive applications) or dual supplies from 4.25 v to 10 v. an on-chip reference provides the correct analog common voltage for single supply applications. both models come in p-dip and so packages. see the ordering guide for more details. * circle surround is a registered trademark of rocktron corporation. ac-3 is a registered trademark of dolby labs, inc. windows is a regis- tered trademark of microsoft corp.
C2C rev. 0 ssm2160/ssm2161Cspecifications (v s = 6 6 v, t a = +25 8 c, a v = 0 db, f audio = 1 khz, f clock = 250 khz, r l = 10 k v , unless otherwise noted) parameter symbol conditions min typ max units audio performance noise floor nfl v in = gnd, bw= 20 khz, a v = 0 db 1 C90 dbu total harmonic distortion + noise thd+n 2nd & 3rd harmonics only, v out = 0 dbu 2 a v = 0 db 0.01 0.035 % channel separation any channel to another 80 db dynamic range nfl to clip point 100 db analog input maximum level v in max v s = 10 v 1.8 v rms impedance z in any channel 10 k w analog output maximum level 3 v s = 10 v, all conditions of master attenuation and channel gain 1.8 v rms impedance z out 10 w offset voltage 20 mv minimum resistive load r l min 10 k w maximum capacitive load c l max 50 pf master attenuator error measured from best fit of all channels from 0 db and C127 db (or noise floor) a v = 0 db channel gain = 0 db 0.5 db a v = C20 db channel gain = 0 db 1.0 db a v = C40 db channel gain = 0 db 2.0 db a v = C60 db channel gain = 0 db 2.5 db channel matching 1.0 db channel gain error master attenuation = 0 db a v = 0 db 0.5 db a v = +10 db 1.0 db a v = +31 db 2.0 db mute attenuation v in = 0 dbu C95 db voltage reference v ref accuracy percent of ( v + ) + ( v ) 2 5% output impedance 5 w control logic logic thresholds high (1) re: dgnd 2.0 v low (0) 0.8 v input current 1 m a clock frequency 1 1000 khz timing characteristics see timing diagrams power supplies voltage range ssm2160 v s single supply +10 +20 v ssm2161 +8.5 +20 v ssm2160 v+, vC dual supply 5 10 v ssm2161 4.25 10 v supply current no load 20 28 ma notes 1 master = 0 db; channel = 0 db. 2 input level adjusted accordingly. 0 dbu = 0.775 v rms. 3 for other than 10 v supplies, maximum is v s /4. specifications subject to change without notice.
ssm2160/ssm2161 C3C rev. 0 timing characteristics timing symbol description min typ max units t cl input clock pulse width, low 200 ns t ch input clock pulse width, high 200 ns t ds data setup time 50 ns t dh data hold time 75 ns t cw positive clk edge to end of write 100 ns t wc write to clock setup time 50 ns t lw end of load pulse to next write 50 ns t wl end of write to start of load 50 ns t l load pulse width 250 ns t w3 load pulse width (3-wire mode) 250 ns notes 1. an idle hi (clk-hi) or idle lo (clk-lo) clock may be used. data is latched on the negative edge. 2. for spi or microwire three-wire bus operation, tie ld to write , and use write pulse to drive both pins. (this generates an automatic internal load signal.) 3. if an idle hi clock is used, t cw and t wl are measured from the final negative transition to the idle state. 4. the first data byte selects an address (msb hi), and subsequent msb lo states set gain/attenuation levels. refer to the address/data decoding truth table. 5. data must be sent msb first. d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 1 1 1 1 clk data write ld t wl t l t lw t dh t ds t ch 0 0 1 1 0 1 1 0 clk data write ld t cl d7 t wc t cw msb figure 1. timing diagrams
ssm2160/ssm2161 C4C rev. 0 absolute maximum ratings 1 supply voltage dual supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v single . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +36 v logic input voltage . . . . . . . . . . . . . . . . . . . . . C0.3 v to +5 v operating temperature range . . . . . . . . . . . . . 0 c to +70 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature range . . . . . . . . . . . . C65 c to +165 c lead temperature range (soldering, 60 sec) . . . . . . . +300 c esd ratings 883 (human body) model . . . . . . . . . . . . . . . . . . . . . . 2.5 kv package thermal information package type 3 u ja u jc units 24-pin plastic p-dip 60 30 c/w 24-pin soic 71 23 c/w 20-pin plastic p-dip 65 26 c/w 20-pin soic 84 24 c/w notes 1 absolute maximum ratings apply at +25 c unless otherwise noted. 2 v s is the total supply span from v+ to vC. 3 q ja is specified for the worst case conditions, i.e., for device in socket for p-dip, packages and for device soldered onto a circuit board for soic packages. ordering guide temperature package package model range description option ssm2160p 0 c to +70 c 24-lead plastic dip n-24 ssm2160s 0 c to +70 c 24-lead sol r-24 SSM2160S-REEL 0 c to +70 c 24-lead sol r-24 ssm2161p 0 c to +70 c 20-lead plastic dip n-20 ssm2161s 0 c to +70 c 20-lead sol r-20 ssm2161s-reel 0 c to +70 c 20-lead sol r-20 pin configurations 24-lead epoxy dip and soic 13 16 15 14 24 23 22 21 20 19 18 17 top view (not to scale) 12 11 10 9 8 1 2 3 4 7 6 5 ssm2160 v+ vout2 mstr set mstr out ch set agnd v ref vout1 vin4 vout4 vin2 vin1 vout3 vin3 vout5 vin5 write data vin6 vout6 ld v clk dgnd 20-lead epoxy dip and soic 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) ssm2161 v+ vout2 mstr set mstr out ch set agnd v ref vout1 vin4 vout4 vin2 vin1 vout3 vin3 write ld v dgnd clk data
ssm2160/ssm2161 C5C rev. 0 pin descriptions s sm2160 ssm2161 pin no. pin no. name function 1 1 v+ v+ is the positive power supply pin. refer to the power supply connections section for more information. 2 2 agnd agnd is the internal ground reference for the audio circuitry. when operating the ssm2160 from dual supplies, agnd should be connected to ground. when operating from a single supply, agnd should be connected to v ref , the internally generated voltage reference. agnd may also be connected to an external reference. refer to the power supply connections section for more details. 33 v ref v ref is the internally generated ground reference for the audio circuitry obtained from a buffered divider between v+ and vC. in a dual-supply application with the agnd pin connected to ground, v ref should be left floating. in a single supply application, v ref should be connected to agnd. refer to the power supply connections section for more details. 4 4 ch1 out audio output from channel 1. 5 5 ch1 in audio input to channel 1. 6 6 ch3 out audio output from channel 3. 7 7 ch3 in audio input to channel 3. 8 C ch5 out audio output from channel 5. 9 C ch5 in audio input to channel 5. 10 8 write a logic low voltage enables the ssm2160 to receive information at the data input (pin 15). a logic high applied to write retains data at their previous settings. see timing diagrams. serves as chip select. 11 9 ld loads the information retained by write into the ssm2160 at logic low. see timing diagrams. 12 10 vC vC is the negative power supply pin. connect to ground if using in a single supply application. refer to the power supply connections section for more details. 13 11 dgnd dgnd is the digital ground reference for the ssm2160. this pin should always be connected to ground. all digital inputs, including write , ld , clk, and data are ttl input compatible; drive currents are returned to dgnd. 14 12 clk clk is the clock input. it is positive edge triggered. see timing diagrams. 15 13 data channel and master control information flows msb first into the data pin. refer to address/ data decoding truth table, figure 19, for information on how to control the vcas. 16 C ch6 in audio input to channel 6. 17 C ch6 out audio output from channel 6. 18 14 ch4 in audio input to channel 4. 19 15 ch4 out audio output from channel 4. 20 16 ch2 in audio input to channel 2. 21 17 ch2 out audio output from channel 2. 22 18 mstr set mstr set is connected to the inverting input of an i-v converting op amp used to generate a master control voltage from the master control dac current output. a resistor connected from mstr out to mstr set reduces the step size of the master control. see the adjusting step sizes section for more details. a 10 m f capacitor should be connected from mstr out to mstr set to eliminate the zipper noise in the master control. 23 19 mstr out mstr out is connected to the output of the i-v converting op amp. see mstr set description. 24 20 ch set the step size of the channel control can be increased by connecting a resistor from ch set to v+. no connection to ch set is required if the default value of 1 db per step is desired. mini- mum of 10 w external resistor. see the adjusting step sizes section for more details.
ssm2160/ssm2161 C6C rev. 0 Ctypical performance characteristics gain ?db ?0 20 ?0 ?0 ?0 0 10 10 1.0 0.1 0.01 0.001 thd+n ?% t a = +25 c v s = 6v v in = 0dbu r l = 10k w c l = 50pf figure 2. thd vs. gain frequency ?hz 0.01 20 30k 100 1k 10k t a = +25 c dual supply operation v in = 300mvrms@1khz r l = 10k w , c l = 50pf master/channel = 0db lpf: < 22khz v s = 12v 0.1 thd+n ?% 0.001 v s = 6v figure 5. thd+n % vs. frequency input voltage ?vrms 0.001 0.01 10 0.1 1 0.1 thd+n ?% 0.01 1.0 t a = +25 c single supply operation v in = sinewave @ 1khz r l = 10k w , c l = 50pf master/channel = 0db v s = 15v v s = 20v v s = 10v figure 3. thd+n % vs. amplitude frequency ?hz ?0 ?0 20 20k 100 1k 10k channel separation ?db ?0 ?0 ?0 ?20 ?0 ?00 ?10 t a = +25 c v s = 6v v in = 1vrms @ 1khz v in = gnd (non selected ch) r l = 100k w , c l = 50pf lpf: < 22khz figure 6. channel separation vs. frequency gain ?db noise ?dbu ?0 ?5 ?10 ?0 ?0 40 ?0 ?0 ?0 ?0 0 10 20 31 ?5 ?0 ?00 ?05 ?0 ?5 ?0 ?5 t a = 25 c v s = 6v v in = gnd figure 8. noise vs. gain input voltage ?vrms 0.5 0.1 0.005 0.05 10 0.1 1 thd+n ?% 0.01 t a = +25 c dual supply operation v in = sinewave @ 1khz r l = 10k w , c l = 50pf master/channel = 0db v s = 12v v s = 5v v s = 6v figure 4. thd+n % vs. amplitude frequency ?hz ?0 ?0 ?0 ?0 ?0 ?20 ?0 ?00 ?10 20 30k 100 output ?db 1k 10k t a = +25 c v s = 6v v in = 1vrms @ 1khz r l = 10k w , c l = 50pf figure 7. mute vs. frequency
ssm2160/ssm2161 C7C rev. 0 frequency ?khz 022 2 4 6 8 10 12 14 16 18 20 0 ?0 ?40 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?20 ?10 ?00 ?30 amplitude ?dbu t a = 25 c v s = 12v vin = 0dbu @ 1khz r l = 100k w master = 20db channel = 0db figure 9a. ths vs. frequency (fft) input amplitude ?vrms 0.1 0.010 0.05 5 0.1 1 0.001 t a = +25 c v s = 12v smpte 4:1 im-freq 60hz/7khz r l = 100k w 0.0001 1md (smpte) ?% figure 10. smpte im vs. amplitude v rms frequency ?khz 022 2 4 6 8 10 12 14 16 18 20 0 ?0 ?40 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?20 ?10 ?00 ?30 t a = 25 c v s = 12v vin = ?1dbu @ 1hz r l = 100k w master = 0db channel = 0db amplitude ?dbu 9b. thd vs. frequency (fft) frequency ?khz 022 2 4 6 8 101214161820 0 ?0 ?40 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?20 ?10 ?00 ?30 amplitude ?dbu t a = 25 c v s = 12v r l = 100k w a master = 0db channel = +31db b master/channel = 0db b a figure 11. noise floor fft supply voltage ?volts 4 13 6 7 8 9 10 11 12 5 25 22 15 supply current ?ma 21 20 19 23 24 18 17 16 figure 13. i sy vs. v s frequency ?khz 022 2468101214161820 0 ?0 ?40 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?20 ?10 ?00 ?30 amplitude ?dbu t a = 25 c v s = 12v vin = ?1dbu @ 1khz r l = 100k w master = 0db channel = 31db figure 9c. thd vs. frequency (fft) frequency ?hz ?0 ?0 20 30k 100 psr ?db 1k 10k ?0 ?0 ?0 ?00 ?0 ?0 ?0 psr psr+ t a = +25 c v s = 6v 10% lpf = <22khz master = 0db channel = 0db figure 12. psr vs. frequency
ssm2160/ssm2161 C8C rev. 0 applications information general the ssm2160 and ssm2161 are six and four channel volume controls intended for multichannel audio applications. while dual channel controls sufficed for stereo applications, the rapidly emerging home theater surround sound and auto sound venues demand both six and four channel high perfor- mance controls. the following information applies equally to the ssm2160 and ssm2161, except where noted. line level signals are fed to the six high impedance inputs. the system microcontroller sets the gain of the six channels via a three or four wire data bus. in a home theater receiver, the outputs may be fed to the power amplifiers or buffered and connected to pre- out/amp-in ports on the rear panel. refer to figure 17 for a typical signal chain using the ssm2160. the master control serves the volume control function, and the channel control serves the balance function. the six channel capability allows complete control of the front left, front right, center, rear left, rear right, and sub-bass audio channels. power supplies vs. signal levels the ssm2160 can be operated from dual supplies from 5v to 10 v and from single supplies from +10 v to +20 v. the ssm2161 can be operated from dual supplies from 4.25 v to 10 v for automotive applications and from single supplies from +8.5 v to +20 v. in order to keep power dissipation to a minimum, use the minimum power supply voltages that will support the maximum input and output signal levels. the peak- to-peak output signal level must not exceed 1/4 of the total power supply span, from v+ to vC. this restriction applies for all conditions of input signal levels and gain/ attenuation settings. table i shows supply voltages for several typical output signal levels for both devices. an on-chip b uffered voltage divider provides the correct analog common voltage for single supply applications. table i. signal levels vs. power supplies ssm2160 max output, max output, v rms (v p-p) dbu single +v s dual 6 v s 0.9 (2.5) +1.3 10 v 5 v 1.1 (3.0) +3.0 12 v 6 v 1.3 (3.7) +4.5 15 v 7.5 v 1.8 (5.0) +7.3 20 v 10 v ssm2161 max output, max output, v rms (v p-p) dbu single +v s dual 6 v s 0.75 (2.1) +1.0 8.5 v 4.25 v 1.1 (3.0) +3.0 12 v 6 v 1.3 (3.7) +4.5 15 v 7.5 v 1.8 (5.0) +7.3 20 v 10 v dual power supplies as shown in figure 14, the agnd pin should be connected to ground and v ref should be left floating. the digital ground pin, dgnd, should always be connected to ground for either single- or dual-supply configurations. pins 1 and 12 should each have a 10 m f capacitor connected to ground, with a 0.1 m f capacitor placed as close as possible to the ssm2160 device to help reduce the effects of high frequency power supply noise. when a switching power supply is used, or if the power supply lines are noisy, additional filtering of the power supply lines may be required. + 1 2 v+ 0.1? 10? v 10? 12 13 dgnd v v ref agnd v+ ssm2160 + 0.1? figure 14. dual supply configuration single power supply when a single supply is used, it is necessary to connect agnd (pin 2) to v ref (pin 3) as shown in figure 15. v ref supplies a voltage midway between the v+ and vC pins from a buffered resistive divider. when supplying this reference to stages ahead of the ssm2160 (to eliminate the need for input dc blocking capacitors, for example), the use of an additional external buffer, as shown in figure 16 may be necessary to eliminate any noise pickup. + + v+ 0.1? 10? 0.1? 10? 3 1 2 12 13 dgnd v v ref agnd v+ ssm2160 figure 15. single supply configuration
ssm2160/ssm2161 C9C rev. 0 + + v+ 0.1? 10? 0.1? 10? 3 1 2 12 13 dgnd v v ref agnd v+ ssm2160 chnin ref out figure 16. single supply operation with v ref buffer signal chain considerations the ssm2160 is capable of providing an extremely wide control range, from C127 db of attenuation (limited only by the noise floor) to +31 db of gain. when configuring the system, the ssm2160 should be in the signal chain where input signals allow the minimum vca gain to be used, thus ensuring the lowest distortion operation. in consumer products, sources that supply line level signals include fm/am tuner, phono preamp, cassette deck, cd, laserdisc, vcr, line, aux and micro- phone preamp. figure 17 shows a typical application where the ssm2160 has been placed between a surround-sound decoder and the power amplification stages. this allows the user to adjust both volume and balance between six speakers through the use of the master and channel controls. fm/am tuner phono preamp cassette deck compact disk laser disk vcr microphone mux surround sound decoder ssm2160 to speakers power amps volume and balance controls line level inputs ?stereo pairs figure 17. typical signal chain using the ssm2160 digital control range plan the ssm2160 may be modelled as six ganged potentiometers followed by individual programmable gain channel amplifiers, as shown in figure 18. in actuality, each channels signal level is set by a vca that can give gain or attenuation, depending upon the control voltage supplied. the input potentiometers have a maximum gain 0 db (unity), a minimum gain of C127 db, and change in 1 db steps. the channel amplifiers each have mini- mum gain of 0 db and a maximum gain of +31 db and also change in 1 db steps. the data settings for the attenuation of the master potentiometer and the channel amplifier are shown in table ii. output channel input 0db ?27db 31db 0db master figure 18. potentiometer representation of ssm2160 (one channel only) table ii. master and channel control data db hex binary master min atten 0 7f 1111111 max atten C127 00 0000000 channel max gain +31 00 00000 midgain +15 10 10000 min gain 0 1f 11111 when using channel controls as balance controls, the center would be with channel = 10 h (or 0f h if desired). increasing the gain to the maximum would occur at channel = 00 h . redu cing the gain to minimum would occur at channel = 1f h . selection address mode address data mode data 7-bit master dac 5-bit channel dac 1 5-bit channel dac 2 5-bit channel dac 3 5-bit channel dac 4 5-bit channel dac 5 5-bit channel dac 6 no dac selected 1 1 1 1 1 1 1 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 x x x x x x x x = "don't care" shaded area is data 0 = mute, 1 = un-mute msb msb lsb lsb xxxxx figure 19. interface characteristics, dac address/data decoding truth table
ssm2160/ssm2161 C10C rev. 0 serial data input format the standard format for data sent to ssm2160 is an address byte followed by a data byte. this is depicted in the truth table, figure 19. two 8-bit bytes are required for each master and each of the six channel updates. the first byte sent contains the address and is identified by the msb being logic high. the second byte contains the data and is identified by the msb being logic low. the 7 lsbs of the first data byte set the attenuation level from 0 db to C127 db for the master. the 5 lsbs of the byte set the channel gain levels from 0 db to 31 db. serial data control inputs the ssm2160 provides a simple 3- or 4-wire serial interface see the timing diagram in figure 1. data is presented to the data pin and the serial clock to the clk pin. data may be shifted in at rates up to 1 mhz (typically). the shift register, clk, is enabled when the write input is low. the write thus serves as a chip select input; however, the shift register contents are not transferred to the holding register until the rising edge of ld . in most cases, write and ld will be tied together, forming a tradition 3-wire serial interface. to enable a data transfer, the write and ld inputs are driven logic low. the 8-bit serial data, formatted msb first, is input on the data pin and clocked into the shift register on the falling edge of clk. the data is latched on the rising edge of write and ld . table iii. input/output levels vs. attenuation/gain input gain/loss output dbu mv rms master channel net dbu mv rms 0 775 C31 31 0 0 775 C31 22 0 31 31 0 775 C28 31 0 31 31 3 1100 saturation prevention unlike a passive potentiometer, the ssm2160 can give up to +31 db of gain, thereby creating a potential for saturating the vcas, resulting in an undesirable clipping or overload condi- tion. careful choice of input signal levels and digital gain parameters will eliminate the possibility. a few of the many acceptable gain and attenuation settings that keep the signals within the pr escribed limits are shown in table iii. the input and output levels are given in mv rms and dbu (0 dbu = 0.775 v rms). line one of the table: the master is not allowed to have less than C31 db attenuation, and the channel is allowed +31 db of gain. since the net gain is zero, there is no possibility of overload with the expected maximum input signal. line two of the table shows that input signal limited to C31 dbu will allow +31 db of channel gain and 0 db of master attenua- tion. with an input below C31 dbu, the output will never exceed 0 dbu, so no overloading is possible. line three of the table allows an input of C28 dbu, master attenuation of 0 db, and 31 db channel gain. the output is a maximum of 3 dbu (1.1 v rms), which is acceptable for power supplies of 6 v or more. so long as v p-p < v supply /4, there will be no overloading (see table i). if unity overall gain is required from the ssm2160, there should be no net gain between the master (loss) and channel (gain), with both at their lowest attenuation position. minimum channel gain is recommended for minimum distortion. master dac channel dac in out r c i fs set summation resistor ? i signal v+ r m c r m , r c , c external ssm2160 figure 20. vca control scheme control range and channel tracking each channel vca is controlled by its own dacs output, plus the control signal from the master dac. this is shown in figure 21. channel dacs are configured to increase the gain of the vca in 1 db steps from zero to 31 db. thus, the midpoint (15, or 16 if you prefer) should be chosen as the center setting of the electronic balance controls. since the master dac feeds all summation nodes, the attenuation of all vcas simulta- neously change from 0 db to the noise floor. maximum attenuation of all channels occurs when the master is set to C127 db attenuation, and the channel is set to 0 db gain. minimum attenuation of all channels occurs when the master is set at 0 db, and the channel is set to +31 db. once the channel to channel balance has been set, the master may be changed without changing the balance. this is shown graphically in figure 21. +31 +16 0 ?6 ?2 ?8 ?4 ?0 ?6 ?12 ?28 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 channel gain channel gain channel gain master attenuation +31 +16 0 +31 +16 0 noise floor 0 0 0 0 0 0 net gain/atten 1 1 1 1 1 1 figure 21. practical control range master/channel step sizes the details of the dac control of the channel vcas is depicted in figure 20. a 7-bit current output dac and an op amp converts the digitally commanded master control level to an analog voltage. a capacitor across the feedback resistor limits the rate of change at the output to prevent clicking. a 5-bit dac converts the digitally commanded channel control level to a voltage via a resistor r. these two control signals sum in resistor r and are fed to the channel vca. although we
ssm2160/ssm2161 C11C rev. 0 present the attenuation and gain as two separate items, in fact, the vca can be operated smoothly from a gain condition to an attenuation. the master and channel step sizes default to 1 db in the absence of external components. the step sizes can be changed by the addition of external resistors if finer resolution is desired. control range vs. step size before adjusting step sizes from the standard 1 db, consider the effect on control range. the master control and the channel control provide 1 db step sizes, which may be modified by the addition of external resistors. as the total number of steps is unchanged, reduction of the step size results in less control range. the range of the control is: range = step size ( db ) ( number of levels used ) since the master volume control operates from a 7-bit word, its dac has 128 levels (including 0). the channel volume control dac is a 5-bit input, so there are 32 levels for volume control (including 0). as can be seen in figure 21, the practical control range is set by the noise floor. it can be advantageous to reduce the master step size to give finer steps from zero attenuation down to the noise floor. reducing master step size to reduce the master step size, place a resistor, r m, between mstr set and mstr out. the master step size of the master volume control will then become: r m = 1700 x master 1 x master where, x master is the desired master control step size in decibels. see figure 22 for practical values of r m . note that the step size for the master control can only be adjusted to less than 1 db. no resistor is required for the default value of 1 db per step. for larger step sizes, use digital control. noninteger db step sizes can be obtained by using digital control and a reduced step size. r master 1.0 0.8 0 10 2 10 5 10 3 master step size ?db 10 4 0.6 0.4 0.2 figure 22. master step size vs. r m example: modifying master step size to 0.5 db a master step size of 0.5 db is desired for the master control, while a 1 db step size is adequate for the channel control. using the above equ ation or figure 22, r m is found to be 1700 w and is connected between mstr set and mstr out. there could be some variation from lot to lot, so applications requiring precise step size should include a fixed plus a trimmer to span the calculated value 25%. in this example, r c is not needed as the default channel step size is already 1 db. ch set is left floating. with this step size, the dynamic range of the master control is: dnr = 0.5 127 db = 63.5 db in this configuration, the maximum master volume is 0 db, while the minimum volume is C63.5 db. since the channel volume can still provide 0 db to 31 db of gain, the total system gain can vary between C63.5 db and 32 db. note that a 0 db command setting to the master control always results in unity gain, regardless of the step size. channel step size the channel dacs full-scale current is set by an internal resistor to the v+. by shunting this resistor, the full-scale current, and therefore the step size, will increase. no provisions are available for reducing the channel step size. to increase the channel step size, place a resistor, r c , from ch set to v+. note that a 0 db setting for a channel will always give unity gain, regardless of how large or small the step size is. this is true for both the master and channel volume controls. r chan 1.5 1.4 1.0 10 1 10 3 10 2 channel step size 1.3 1.2 1.1 figure 23. channel step size vs. r c example: modifying channel step size a channel step size of 1.3 db is desired. from figure 23 we see that a 40 w resistor (approximately) connected from ch set to v+ is required. as this varies from lot to lot, the exact value should be determined empirically, or a fixed resistor plus trimmer potentiometer should be used . take care not to short pin 24 to pin 1 as damage will result. muting the ssm2160 offers master and channel muting. on power up, the master mute is activated, thus preventing any transients from entering the signal path and possibly overloading amplifi- ers down the signal path. mute is typically better than C95 db relative to a 0 dbu input. due to design limitations, the individual channel muting results in increased signal distortion in the unmuted channels. users should determine if this condition is acceptable in the particular application.
ssm2160/ssm2161 C12C rev. 0 dc blocking and frequency response all internal signal handling uses direct coupled circuitry. although the input and output dc offsets are small, dc blocking is required when the signal ground references are different. this will be the case if the source is from an op amp that uses dual power supplies (i.e., 6 v), and the ssm2160 uses a single supply. if the signal source has the capability of operating with an externally supplied signal, connect the v ref (pin 3) to the sources external ground input either directly or through a buffer as shown in figure 16. the same consideration is applied to the load. if the load is returned to agnd, no capacitor is required. when the ssm2160 is operated from a single supply, there will be a dc output level of +v s /2 at the output. this will require dc blocking capacitors if driving a load referred to gnd. when dc blocking capacitors are used at the inputs and outputs, they form a high pass filter with the input and load resistance both of which are typically 10 k w . to calculate the lower C3 db frequency of the high-pass filter formed by the coupling capacitor and the input resistance, use the following formulas: f c = 1/(2 p rc) , or c = 1/(2 p r f c ) where r is the typically 10 k w input resistance of the ssm2160 or the load resistance. c is the value of the blocking capacitor when f c is known. if a cutoff frequency of 20 hz were desired, solving for c gives 0.8 m f for the input or output capacitor. a higher load imped- ance will allow smaller output capacitors to give the same 20 hz cutoff. note that the overall low-pass filter will be the cascade of the two, so the response will be C6 db at 20 hz. a practical and economical choice would be 1 m f/15 v electrolytics. signal/noise considerations and channel center gain the ssm2160 should be placed in the signal flow where levels are high enough to result in low distortion and good snr, but not so high to require unusually high power supplies. in a typical application, input and output signal levels will be in the 300 mv 200 mv rms range. this level is typically available from internal and external sources. as previously mentioned, the +31 db of gain available in the vca is usually used for balancing the various channels and is usually set to +15 db or +16 db in its center position. due to the nature of vcas performance vs. gain, the minimum gain that will allow balanc- ing the channels should be used. if no balance function is required, the channel gain should be set to 0 db. use the lowest value of centered gain when less than the full balance range is needed. for example, if only 6 db channel gain variations were needed, the center could be set at +6 db, giving +6 db 6 db, rather than at +15 db 6 db. this would result in improved s/n ratio and less distortion. digital interface digital logic signals have fast rising and falling edges that can easily be coupled into the signal and ground paths if care is not taken with pc board trace routing, ground management, and proper bypassing. in addition, limiting the high state logic signal levels to 3.5 v will minimize noise coupling. load considerations the output of each ssm2160 channel must be loaded with a minimum of 10 k w . connecting a load of less than 10 k w will result in increased distortion and may cause excessive internal heating with possible damage to the device. capacitive loading should be kept to less than 50 pf. excessive capacitive loading may increase the distortion level and may cause instability in the output amplifiers. if your application requires driving a lower impedance or more capacitive load, use a buffer as shown in figure 24. vout 1 vout 6 ssm2160 ch1 out ch6 out 1/2 ssm2135 1/2 ssm2135 figure 24. output buffers to drive capacitive loads windows software windows software is available to customers from analog devices to interface the serial port of a pc (running windows 3.1) with the ssm2160. contact your sales representative for details on obtaining the software. for more details, see the evaluation board section. 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 ssm2160 + 0.1? 10? + 0.1? 10? + 10? r m * out in ch 2 out in ch 4 out in ch 6 data clk out in ch 1 out in ch 3 out in ch 5 v write ld v+ * *optional see ?tep size **typical 1?0?: see ?.c. blocking r c * ** figure 25. typical application circuit (dual supply)
ssm2160/ssm2161 C13C rev. 0 controlling stereo headphones level and balance figure 26 shows how the ssm2160 can be configured to drive a stereo headphone output amplifier. note that the minimum load specification precludes driving headphones directly. this example assumes that audio left and right signals are being fed into channels 1 and 2, respectively. additional amplifiers could be connected to the outputs to provide additional channels. the master control will set the loudness, and the channel controls will set the balance. the headphone amplifiers may be connected to the same power supplies as the ssm2160. the stereo audio signals are directly coupled to the noninverting input of both op amps. depending upon the headphones and the signal levels, the optional r1 may be selected to provide additional gain. the gain is determined by: a v = 1 + r 2 r 1 ? ? ? ? as an example, suppose a high impedance headphone (600 w ) required a minimum of 25 mw to produce the desired loudness. further, suppose the system design made available an output level from the ssm2160 of 300 mv. if the output were buffered without gain and applied directly to the headphone, the power would be: p = v 2 r p = (0.3) 2 600 = 0.15 mw this is obviously too little power, so we solve the equation for the voltage required to produce the desired power of 25 mw: v = pr v = 0.025 600 = 3.9 v rms the gain of the amplifiers must then be: a v = 3. 89 0. 3 = 13 a v = 1 + r 2 r 1 r 2 r 1 = 12 r 1 = r 2 12 = 6000 12 = 500 w if lower impedance headphones were used, say 30 w , the voltage required would be 0.9 v rms, so a gain of 3 would suffice, thus r1 = 2.5 k w and r2 = 5 k w . the 100 pf capacitor, c 2 , in parallel with r2, creates a low- pass filter with a cutoff above the audible range, reducing the gain to high frequency noise. a small resistor within the feedback loop protects the output stage in the event of a short circuit at the headphone output but does not measurably reduce the signal swing or loop gain. the dc blocking capacitor at the output establishes a high pass filter with a C3 db corner fre- quency determined by the value of c1 and the headphone impedance. with 600 w headphones, an output capacitor of 15 m f sets this corner at 20 hz. similarly, a 30 w headphone will require 250 m f. caution: as with all headphone applications, listening to loud sounds can cause permanent hearing loss. +5v ?5v ch1out ch2out v dgnd v+ agnd ssm2160 ssm2135-a ssm2135-b +5v + ?v + r 1 * 500 w r 1 * 500 w c2 100pf r 2 6k w 150 w 150 w r 2 6k w c2 100pf +5v ?5v 50k w 50k w 15?* 15?* left headphone 600 w right headphone 600 w *see text for alternate values 1 2 4 21 12 13 figure 26. headphone output amplifier configuration evaluation board for the ssm2160 the following information is to be used with the ssm2160 evaluation board, which simplifies connecting the part into existing systems. audio signals are fed in and out via standard rca-type audio connectors. a stereo headphone driver socket is provided for the convenience of listening to channels 1 and 2. microsoft windows software is available for controlling the serial data bus of the ssm2160 via the parallel port driver (lpt) of an ibm-compatible pc. the software may be downloaded from the analog devices internet web site at http://www.analog.com, or by requesting a diskette from analog audio marketing by faxing (408)727-1550. the demo board comes complete with the necessary parallel port cable and telephone type plug that mates with the evaluation board. power supplies the demo board should be connected to 6 v supplies for initial evaluation. if other supply voltages are planned, they can be subsequently changed. the power configuration on the evaluation board is per figure 14. signal inputs and outputs input load impedances are approximately 10 k w , so the load on the sources is relatively light. dc blocking capacitors are provided on the evaluation board. the load impedance connected to the outputs must be no less than 10 k w and no more than 50 pf shunt capacitance. this enables driving short lengths of shielded or twisted wire cable. if heavier loads must be driven, use an external buffer as shown in figure 25. note that 50 w isolation resistors are placed in series with each ssm2160 output and may be jumpered if desired. digital interface the interconnecting cable provided has a db25 male connector for the parallel port of the pc and an rj14 plug that connects to the evaluation board. this cable is all that is required for the computer interface. software installation if installing the software from a diskette, and using windows version 3.1 or later, select the run command from the file menu of the program manager. in the command line, type a:\setup and press return. if you downloaded the software to
ssm2160/ssm2161 C14C rev. 0 your hard disk from the analog devices website to, say, c:\ssm2160, on the command line type c:\ssm2160\setup and press return. the software will be automatically installed and a ssm2160 start-up icon will be displayed. double-click the icon to start the application. under the menu item port, select the parallel port that is assigned to the connector used on your pc if different from the default lpt1. windows control panel the control panel contains all the functions required to control the ssm2160, and each feature will be described below. a mouse is needed to operate the various controls. it is possible to overload the vca (voltage controlled amplifier) by incor- rect input levels, master and control settings. if you have not read the sections of the data sheet regarding control planning, do so now. while no damage will occur to the ssm2160, the results will be unpredictable. master volume the master volume fader controls the 7-bit word that deter- mines the attenuation level. there are 128 levels (2 7 ) that range from zero db attenuation through C127 db attenuation. to change the level, simply click the up or down arrows or click in the space directly above or below the fader knob, or drag the knob up or down to its desired position. (drag refers to placing the screen cursor arrowhead on the control, pressing and holding the left mouse button while moving the arrow to the desired position.) master mute below the master volume fader is the master mute button. click this button to mute all channels. clicking it again will unmute all channels. the application defaults to mute when started. mute reduces outputs to approximately C95 db below inputs up to 0 dbu. channel volume each of the channel fader controls can be set to one of 32 levels of gain, from 0 db to +31 db. see master volume above for details. channel mute same function as master mute but on a channel basis. due to the design limitations, muting an individual channel results in an increased distortion level of the unmuted channels. users must determine if this condition is acceptable in their applica tion. channel balance the channel balance fader adjusts all channels over their range without affecting the master volume setting. relative channel differences will be maintained until the top or the bottom of the range is rea ched. the master volume fader does the same function as this fader, which was made available for evaluation convenience. fades both master and channel fades can be achieved by pressing the mem 1 button when levels are at a desired starting position and the mem 2 button at the desired ending position. fade controls individual channels and master fade, the master volume. fade time sets timing from 0.1 (fastest) to 9.9 (slowest). press fade to commence operation. if fade is pressed again, a fade back to the starting point will occur. the jump button causes a direct jump to the opposite memory position. halt halt is a software interrupt in case of a problem, or to stop a long fade time. update data currently on display is resent to the ssm2160. this is useful when parts are being substituted in the evaluation board, or when the interface cable is changed. should you have any questions regarding the evaluation board or the ssm2160, please contact the analog audio group applications specialist at (408)562-7520.
ssm2160/ssm2161 C15C rev. 0 ssm2160 20-lead sol (r-20) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 20 11 10 1 0.5118 (13.00) 0.4961 (12.60) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 24-lead plastic di p (n-24) 24 112 13 0.280 (7.11) 0.240 (6.10) pin 1 1.275 (32.30) 1.125 (28.60) 0.150 (3.81) min 0.200 (5.05) 0.125 (3.18) seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) ssm2161 20-lead plastic dip (n-20) 20 110 11 1.060 (26.90) 0.925 (23.50) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 24-lead sol (r-24) 24 13 12 1 0.6141 (15.60) 0.5985 (15.20) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 outline dimensions dimensions shown in inches and (mm).
C16C c2214C6C10/96 printed in u.s.a.

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